AHA’s Forward Error Correction codecs offer a high level of cost-effective error correction performance. Some of the designs stem from research completed for NASA space communications. AHA has integrated all Reed-Solomon encoding/decoding and specific controller functions into single, low-cost VLSI chips for on-the-fly error/erasure correction.
The AHA4013 provides proven Reed-Solomon error correction using the standard Intelsat IESS-308 polynomial. It offers programmable error correction capabilities from 1 to 10 errors and from 2 to 20 erasures. It can reach a data throughput of 100 Mbit/sec.
AHA offers Reed-Solomon cores that meet the ITU G.709 standard and operate at 10 Gigabit and 40 Gigabit payload data rates. The cores support the 16 block interleaved RS(255,239) code specified in Annex A of the G.709 standard. The cores require no configuration, no initialization, and no resynchronization procedures. Small die size, low power, and complete Bit Error Rate reporting are also key features of these cores. One clock edge synchronous design that is also free of multi-cycle paths simplify implementation and verification.
AHA also offers non-interleaved 2.5 Gigabit Reed-Solomon encoder and decoder cores that implement the same RS(255,239) code specified in the G.709 standard.
|AHA4013||12.5 MBytes/sec Reed-Solomon Error Correction IC|
|G709D-10||10 Gbits/sec ITU G.709 Reed-Solomon Decoder Core|
|G709D-40||40 Gbits/sec ITU G.709 Reed-Solomon Decoder Core|
|G709D2-5||2.5 Gbits/sec ITU G.709 Reed-Solomon Decoder Core|
|G709E2-5||2.5 Gbits/sec ITU G.709 Reed-Solomon Encoder Core|