The AHA4702DHS-SB FEC decoder core is compliant with section 5.3 of the Digital Video Broadcast S2 (DVB-S2) standard for short frame blocks (16K). It is capable of 600 Mbit/sec user data rate with a 2/3 rate LDPC Code and 25 iterations in an Altera Stratix IV FPGA. The core supports all codes and symbol interleave schemes for short frame blocks specified in the DVB-S2 specification for broadcast, interactive, digital satellite news gathering, and professional services. The core allows code and modulation changes on a block-by-block basis to fully support both Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM).
  • DVB-S2 compliant Short Frame (16K) only
  • LDPC inner code with BCH outer code
  • 400 Msymb/sec channel rate
  • 600 Mbit/sec data rate with a 2/3 rate code and 25 iterations using a Stratix IV FPGA
  • Available for Multiple FPGA Vendors/families
  • Supported codes:  1/4 through 8/9 code rates
  • Supported block sizes:  16K
  • Packet Error Rate performance to 1E-7
  • Auto Iterations to optimize code performance
  • Full ACM and VCM compliance


  • Synthesized netlist
  • Simulation netlist
  • Product specification
Product Briefs


Data Compression

Forward Error Correction

Encryption and Hashing

Regular Expression Search

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