Turbo Product Code (TPC) Encoder Core
The AHA4502E Turbo Product Code encoder IP core is intended for both FPGA based and ASIC based products. The core is configurable allowing a broad range of code rates and correction power. Data interfaces consist of one bit serial in and out of the encoder. Both the input and output data interfaces use a synchronous handshake transfer protocol. The core design uses one clock, rising edge only. Possible replacement for the obsolete AHA4524 device.
  • Constituent code selection for each axis, X, Y, and Z
  • Max channel rate of 150 Mbit/sec FPGA
  • Max user data rate of 134 Mbit/sec FPGA
  • Support for external synchronization
  • Maximum unshortened block size is 16384 bits encoded
  • Simulation and system level modeling software tools available


  • FPGA or ASIC library based netlist
  • Product Specification
  • Bit accurate C models
  • Software Simulator 
Product Briefs

Product Specifications
AHA4502E Specification - TPC Encoder Core


Data Compression

Forward Error Correction

Encryption and Hashing

Regular Expression Search

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