Turbo Product Code (TPC) Decoder Core
The AHA4502D Turbo Product Code decoder IP core is intended for both FPGA based and ASIC based products.  The core is configurable allowing a broad range of code rates and correction power.  Data interfaces consist of one soft metric per clock into the decoder and one-bit serial out of the decoder, and both input and output data interfaces use a synchronous handshake transfer protocol.  The core design uses one clock, rising edge only.  Number of iterations can be constant or variable allowing the device to stop iterating early if no more iterations are required.  Status output allows monitoring of correction performance. Possible replacement for the obsolete AHA4524 device.
  • Constituent code selection for each axis, X, Y, and Z
  • Max channel rate of 38 Mbit/sec FPGA
  • Max user data rate of 34 Mbit/sec FPGA
  • Latency while streaming is 2 block times
  • Support for external synchronization
  • Maximum unshortened block size is 16384 bits encoded
  • Simulation and system level modeling software tools available
  • Up to 4 bits of soft decision resolution per soft metric


  • FPGA or ASIC library based netlist
  • Product Specification
  • Bit accurate C models
  • Software Simulator 
Product Briefs

Product Specifications
AHA4502D Specification - TPC Decoder Core


Data Compression

Forward Error Correction

Encryption and Hashing

Regular Expression Search

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