AHA4702DHS
DVB-S2 Compliant LDPC/BCH Forward Error Correction (FEC) Decoder Core
 
The AHA4702DHS FEC decoder core is fully compliant with section 5.3 of the Digital Video Broadcast S2 (DVB-S2) standard.  It is capable of 600 Mbit/sec user data rate with a 2/3 rate LDPC Code and 25 iterations in a Stratix IV FPGA.  The core supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2 specification for broadcast, interactive, digital satellite news gathering, and professional services.  The core allows code and modulation changes on a block-by-block basis to fully support both Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM).
 
Features
  • DVB-S2 compliant
  • LDPC inner code with a BCH outer code
  • 400 Msymb/s channel rate
  • 600 Mbit/sec data rate a with 2/3 rate code
    and 25 iterations using a Stratix IV FPGA
  • Supported codes: 1/4 through 9/10 code rates
  • Supported block sizes: 16K and 64K block sizes
  • Packet Error Rate performance to 10E-7
  • Auto Iterations to optimize code performance
  • Full ACM and VCM compliance

Deliverables

  • Synthesized netlist
  • Simulation netlist
  • Product specification 
Product Briefs

Product Specifications
AHA4702DHS Specifications - DVB-S2 Compliant LDPC/BCH FEC Decoder Core

Evaluation Tools
LDPC Evaluation Software - Linux
LDPC Evaluation Software - Windows

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Data Compression

Forward Error Correction

Encryption and Hashing

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