DVB-S2 Compliant LDPC/BCH Forward Error Correction (FEC) Encoder Core
The AHA4702ES FEC encoder core is fully compliant with section 5.3 of the Digital Video Broadcast S2 (DVB-S2) standard. It is capable of 5 Mbit/sec user data rate with a 2/3 rate LDPC Code in an Xilinx Virtex V FPGA. This configuration uses 284 slices and 12 block RAMS. The core supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2 specification for broadcast, interactive, digital satellite news gathering, and professional services. The core allows code and modulation changes on a block-by-block basis to fully support both Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM).
- DVB-S2 compliant
- LDPC inner code with a BCH outer code
- Supported codes: 1/4 through 9/10 code rates
- Supported block sizes: 16K and 64K block sizes
- Packet Error Rate performance to 10E-7
- Full ACM and VCM compliance
- FPGA synthesized netlist.
- Simulation netlist