DVB-S2 Compliant LDPC/BCH Forward Error Correction (FEC) Decoder Core
The AHA4702DS FEC decoder core is fully compliant with section 5.3 of the Digital Video Broadcast S2 (DVB-S2) standard.  It is capable of 7.2 Mbit/s channel rate with a 2/3 rate LDPC code and 25 iterations in a Xilinx Virtex V FPGA. This configuration uses 2103 slices and 120 block RAMs.  The core supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2 specification for broadcast, interactive, digital satellite news gathering, and professional services.  The core allows code and modulation changes on a block-by-block basis to fully support both Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM).
  •  DVB-S2 compliant
  • LDPC inner code with a BCH outer code
  • Supported codes: 1/4 through 9/10 code rates
  • Supported block sizes: 16K and 64K block sizes
  • Packet Error Rate performance to 10E-7
  • Full ACM and VCM compliance
  • 7.2Mbit/s channel rate, 2/3 code, 150MHz
  • 2103 slices, 120 block RAM, Virtex V


  • Synthesized netlist
  • Simulation Netlist
  • Product Specification
Product Briefs

Product Specifications
AHA4702DS Specification - DVB-S2 Compliant LDPC/BCH FEC Decoder Core

Evaluation Tools
LDPC Evaluation Software - Linux
LDPC Evaluation Software - Windows


Data Compression

Forward Error Correction

Encryption and Hashing

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