DVB-S2 Compliant LDPC/BCH Forward Error Correction (FEC) Decoder Core
The AHA4702D FEC decoder core is fully compliant with section 5.3 of the Digital Video Broadcast S2 (DVB-S2) standard.  It is capable of 200 Mbit/sec user data rate with a 2/3 rate LDPC Code and 25 iterations in an ASIC.  The core supports all codes, frame sizes, and interleave schemes set forth in the DVB-S2 specification for broadcast, interactive, digital satellite news gathering, and professional services.  The core allows code and modulation changes on a block-by-block basis to fully support both Adaptive Coding and Modulation (ACM) and Variable Coding and Modulation (VCM).
  • DVB-S2 compliant
  • LDPC inner code with BCH outer code
  • 64 Msymb/s channel rate
  • Supported codes:  1/4 through 9/10 rates
  • Supported block sizes:  16K and 64K
  • Packet Error Rate performance to 10E-7
  • Auto Iterations to optimize code performance
  • Full ACM and VCM compliance 


  • FPGA or ASIC synthesized netlist
  • Complete documentation
  • Bit accurate C models
Product Briefs

Product Specifications
AHA4702D Specification - DVB-S2 Compliant LDPC/BCH FEC Decoder Core
LDPC Simulation Tool Kit User's Guide

Evaluation Tools
LDPC Evaluation Software - Linux
LDPC Evaluation Software - Windows


Data Compression

Forward Error Correction

Encryption and Hashing

Regular Expression Search

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